Low current substrate bias generator

ABSTRACT

A low current substrate bias generator for regulating the voltage of a substrate layer of an integrated circuit includes a sense circuit having an input for sensing the voltage of the substrate and an output that is coupled to an inverter for providing a control signal. The control signal controls a charge pump that is coupled to the substrate layer or well that is desired to be regulated. The sense circuit includes a load element and a level shifting circuit having a predetermined standing current requirement that flows directly into the substrate. The current requirement of the bias generator is reduced by increasing the value of the load element and a reasonable delay time is maintained by coupling a capacitor across the level shifting circuit. Since the voltage across the capacitor cannot be changed instantaneously, changes in the substrate voltage are directly coupled from the input to the output of the sense circuit, triggering the charge pump. Regulation of the substrate voltage level proceeds with no corresponding increase in delay time.

BACKGROUND OF THE INVENTION

This invention relates generally to bias generator circuits forgenerating a bias voltage for a semiconductor substrate layer of anintegrated circuit, and more particularly to a circuit and method forreducing the amount of standing current required by the bias generator.

A technique for improving the performance of an integrated circuitformed on a substrate such as a memory device is to provide a separatebias voltage to the substrate instead of coupling the substrate to thefive volt power supply (V_(DD)) or ground, as appropriate. The value ofthe bias voltage is negative for P-type substrates or wells and isgreater than V_(DD) for N-type substrates or wells. The substrate biasvoltage is typically generated with an on-chip circuit containing acharge pump. When the substrate or well voltage changes from a nominalvalue due to a change in the operating condition of the integratedcircuit, a sense circuit provides a control voltage to turn on thecharge pump. In turn, the charge pump pumps charge into or out of thesubstrate until the substrate or well voltage returns to the nominalvalue. The sense circuit then provides a control voltage to turn off thecharge pump.

Prior art bias generator circuits draw a significant standing currentthat flows directly into the substrate. This standing current directlyand indirectly increases the power requirements of the bias generatorcircuit. In the case of a P-type substrate or well, the additionalcurrent raises the substrate voltage. Therefore, the charge pump must beturned on more frequently to maintain a nominal substrate voltage. Sincethe charge pump is typically only 25-35% efficient, an additional 1 μAof current flowing in the sense circuit translates to an additional 3-4μA of current that must be consumed by the charge pump. Typically, 5 μAof current is required by the sense circuit to maintain a reasonablyshort delay time to respond to changes in the substrate voltage. Thus, atotal of 20-25 μA of additional standby current is consumed by the biasgenerator circuit.

One simple way to reduce the current requirements of the bias generatorcircuit is to decrease the current flowing through the sense circuit.Such a decrease in current, however, produces a correspondingundesirable increase in the delay time in response to changes in thesubstrate voltage. Thus, the accuracy of the regulated substrate voltagedecreases resulting in decreased performance and, possibly, latch-up ofthe integrated circuit.

What is desired is a bias generator circuit for regulating the voltageof a substrate on an integrated circuit having a low standing currentrequirement yet maintaining a reasonable delay time in responding tochanges in the substrate voltage.

SUMMARY OF THE INVENTION

The present invention is a low current substrate bias generator forregulating the voltage of a substrate layer of an integrated circuit.The bias generator includes a sense circuit having an input for sensingthe voltage of the substrate and an output that is coupled to aninverter for providing a control signal. The control signal controls acharge pump that is coupled to the substrate layer or well that isdesired to be regulated. The sense circuit includes a load element and alevel shifting circuit having a predetermined standing currentrequirement that flows directly into the substrate. The currentrequirement of the bias generator is reduced by increasing the value ofthe load element and a reasonable delay time is maintained by coupling acapacitor across the level shifting circuit. Since the voltage acrossthe capacitor cannot be changed instantaneously, changes in thesubstrate voltage are directly coupled from the input to the output ofthe sense circuit, triggering the charge pump. Regulation of thesubstrate voltage level proceeds with no corresponding increase in delaytime.

The foregoing and other objects, features and advantages of theinvention will become more readily apparent from the following detaileddescription of a preferred embodiment that proceeds with reference tothe drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a substrate bias generator circuitaccording to the present invention for maintaining the substrate voltageof a P-type substrate or well.

FIG. 2 is a timing diagram illustrating the time response of thesubstrate bias generator of the present invention.

FIG. 3 is a schematic diagram showing charge sharing of changes in thesubstrate voltage.

FIG. 4 is a schematic diagram of a substrate bias generator circuitaccording to the present invention for maintaining the substrate voltageof an N-type substrate or well.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Referring now to FIG. 1, a low current substrate bias generator 10 forregulating the voltage V_(BB) of a substrate layer of an integratedcircuit according to the present invention includes a bias output node28 for coupling to the substrate layer or well. The bias output node 28also serves as the input to a sense circuit that includes a load element12 and a level shifting circuit 14 that are coupled together at anintermediate node 26. The voltage on the intermediate node 26 isdesignated V_(A). The load element 12 is coupled between theintermediate node 26 and the positive five volt supply voltage source,V_(DD). The level shifting circuit 14 is coupled between theintermediate node 26 and the bias output node 28. A capacitor 16 havinga value of C1 is also coupled between the intermediate node 26 and thebias output node 28. An inverter 18, 20 includes an N-channel inputswitching FET 20 and a P-channel load FET 18. The input of the inverter18, 20 is coupled to the intermediate node 26. The output of theinverter 18, 20 is coupled to a hysteresis circuit element 22 such as abuffer amplifier, inverter, or the like. A charge pump 24 has an inputcoupled to the output of the hysteresis circuit element 22 and an outputcoupled to the bias output node 28.

In operation, the bias generator 10 regulates the substrate voltageV_(BB) to a voltage between 0 and -2 volts. A typical nominal level forthe substrate voltage V_(BB) is -1.2 volts, but the actual level dependson the design of the integrated circuit. The number and size of diodesD1 through DN of the level shifting circuit 14 are selected such thatswitching FET 20 is just barely off if the substrate voltage is at thenominal level. If the nominal substrate voltage changes to a morepositive level such as -0.8 volts due to the change in operating statusor environmental conditions of the integrated circuit, a portion of thischange is directly coupled to the intermediate node 26 via capacitor 16.Thus, the inverter 18, 20 changes state and a logic zero is presented tothe hysteresis circuit element 22. A control signal CPEN (charge pumpenable) is provided at the output of the hysteresis circuit element 22that turns on the charge pump 24 to restore the nominal substratevoltage. Once the substrate voltage V_(BB) is restored to the nominallevel, the voltage V_(A) on intermediate node 26 returns to a level justbelow the switching threshold of the inverter 18, 20. The inverter 18,20 and control signal CPEN change state and the charge pump is turnedoff.

The time response of the bias generator 10 is shown in FIG. 2. Thesubstrate voltage V_(BB) is shown as a step ΔV_(BB) from a nominalvoltage to a voltage sufficient to change the logic state of theinverter 18, 20 and to turn on the charge pump 24. The voltage V_(A1) atintermediate node 26 represents the voltage response without capacitor16 for three different values of impedance 12. Due to the parasiticcapacitance at intermediate node 26, a low value of impedance 12produces a short time constant and a quick response as shown in waveform30. A higher value of impedance 12 produces a longer time constant and aslower response as shown in waveform 32. A still higher value ofimpedance 12, while significantly decreasing the value of the standingcurrent I_(S), produces a still longer time constant and a much slowerresponse as shown in waveform 34. The dashed line labeled CPEN THRESHOLDrepresents the level at which the inverter 18, 20 switches and turns onthe charge pump 24. Note that the delay time progressively increases inwaveforms 30-34 as the value of the impedance 12 increases.

The voltage V_(A2) at intermediate node 26 represents the voltageresponse including capacitor 16 for an extremely high value of impedance12 and a correspondingly low value of I_(S). Since the voltage acrosscapacitor 16 cannot be changed instantaneously, changes in the substratevoltage V_(BB) are directly coupled from the input 28 to the output 26of the sense circuit 12, 14. Note that there is no increase in the delaytime, although V_(A2) increases slowly after the CPEN THRESHOLD iscrossed. The increase due to the long time constant is shown in waveformportion 36. The slope of ΔV_(A2) and time at which V_(A2) crosses theCPEN THRESHOLD is determined primarily by the slope of ΔV_(BB). However,the magnitude of ΔV_(A2) is not exactly equal to ΔV_(BB).

FIG. 3 shows the charge sharing of the substrate voltage V_(BB). Thevoltage on capacitor 16 having a value of C1 cannot be changedinstantaneously, but the charge on capacitor 16 must be shared with theparasitic capacitors 42, 44, and 46 designated C_(Z), C₁₄, and C₂₀,respectively. Parasitic capacitors 42, 44, and 46 represent theparasitic capacitance of the load element 12, the level shifting circuit14, and the input to the switching FET 20. If the total parasiticcapacitance has a value of CS, then the magnitude of the change inV_(A2) is given by:

    ΔV.sub.A2 =ΔV.sub.BB ×(Cl/(Cl +CS)).

For example, if the total parasitic capacitance has a value of 0.2 pfand the value of capacitor 16 is 1.8 pf, then 90% of the change insubstrate voltage is coupled to intermediate node 26.

Referring back to FIG. 1, the sense circuit including load element 12and level shifting circuit 14 has a predetermined standing current I_(S)that flows directly into the substrate. The current requirement of thebias generator 10 is reduced by increasing the value of the load element12 and a reasonable delay time is maintained by coupling a capacitor 16across the level shifting circuit 14. For a significant reduction in thecurrent requirements of bias generator 10, the value of the load element12 can exceed 10 Megohms. Therefore, the current flowing through loadelement 12 can be less than the typical 5 μA. A reduced current flow of1 μA or less may easily be achieved. Theoretically, the current flowingthe sense circuit 12, 14 can be as low as several tens of picoamps. Ahigh value of resistance for load element 12 is possible by using alightly doped polysilicon resistor, an undoped polysilicon resistor, aserpentine N-type well in a P-type substrate, a serpentine P-type wellin an N-type substrate or the drain-to-source resistance of anappropriately sized FET.

The level shifting circuit 14 includes a plurality of serially-connecteddiodes D1 through DN. The diodes D1 through DN can be diode-connectedP-channel FETs, diode-connected N-channel FETs, or a combination of thetwo. Similarly, the capacitor 16 can be a P-channel or N-channel FETwherein the gate forms a first plate of the capacitor, and the coupledsource and drain forms the second plate of the capacitor. To provide achange in the voltage ΔV_(A) that is approximately equal to the changein the substrate voltage ΔV_(BB), it is desirable that the capacitor 16be selected to be between five and ten times the combined parasiticcapacitance CS of the load element 12, level shifting circuit 14, andswitching FET 20. For example, if the total parasitic capacitance has avalue of 0.2 pf, it is desirable that capacitor 16 be selected to bebetween 1 pf and 2 pf.

As is known in the art, it is desirable to add hysteresis to theswitching of the inverter 18, 20 in order that the charge pump is notexcessively cycled. Therefore, a hysteresis circuit element 22 such asan inverter, buffer amplifier or the like can be inserted between theoutput of the inverter 18, 20 and the input of the charge pump 24.Alternatively, the inverter 18, 20 can be configured to include ahysteresis switching-threshold. It is also desirable that the switchingFET 20 and the load FET be sized for high gain such that a small changeat the input switches the inverter. Therefore, the size of the inputswitching FET 20 can be at least ten times the size of the load FET 18.

If an integrated circuit is built on an N-type substrate or containsN-type wells, performance is enhanced by generating a bias voltage thatis greater than V_(DD). Referring now to FIG. 4, a low current substratebias generator 50 for regulating the voltage V_(HI) of a substrate layerof an integrated circuit containing an N-type substrate or well includesa bias output node 68 for coupling to the substrate layer or well. Thebias output node 68 also serves as the input to a sense circuit thatincludes a load element 52 and a level shifting circuit 54 that arecoupled together at an intermediate node 66. The voltage on theintermediate node 66 is designated V_(A). The load element 52 is coupledbetween the intermediate node 66 and ground. The level shifting circuit54 is coupled between the intermediate node 26 and the bias output node68. A capacitor 16 having a value of C1 is also coupled between theintermediate node 66 and the bias output node 68. An inverter 58, 60includes a P-channel input switching FET 58 and an N-channel load FET60. The input of the inverter 58, 60 is coupled to the intermediate node66. The output of the inverter 58, 60 is coupled to a hysteresis circuitelement 62 such as a buffer amplifier, inverter, or the like. A chargepump 64 has an input coupled to the output of the hysteresis circuitelement 62 and an output coupled to the bias output node 68.

In operation, the operation of bias generator 50 is similar to that ofbias generator 10 described above with the exception that the chargepump 64 must be designed to provide a voltage V_(HI) that is greaterthan V_(DD). In both bias generator 10 and 50 it is desirable that thetermination of capacitor 16, 56 and level shifting circuit 14, 54 at thebias output node 28, 68 be physically located as close as is possible onthe integrated circuit. This is especially important in highly resistivesubstrates.

Having illustrated and described the principles of my invention in apreferred embodiment thereof, it should be readily apparent to thoseskilled in the art that the invention can be modified in arrangement anddetail without departing from such principles. I claim all modificationscoming within the spirit and scope of the accompanying claims.

I claim:
 1. A low current substrate bias generator for regulating themagnitude of the nominal voltage of a substrate layer in an integratedcircuit comprising:a bias output node for coupling to the substratelayer; an intermediate node; a load element coupled between theintermediate node and a source of supply voltage; a level shiftingcircuit coupled between the intermediate node and the bias output node;an inverter having an input and an output, the input being coupled tothe intermediate node; a charge pump having an input coupled to theoutput of the inverter and an output coupled to the bias output node;and a capacitor coupled between the intermediate node and the biasoutput node for directly coupling changes in the voltage of thesubstrate layer to the intermediate node sufficient to turn on thecharge pump and return the voltage of the substrate layer to the nominalvalue.
 2. A low current substrate bias generator as in claim 1 in whichthe value of the load element exceeds 10 Megohms.
 3. A low currentsubstrate bias generator as in claim 2 in which the load elementcomprises a lightly doped polysilicon resistor.
 4. A low currentsubstrate bias generator as in claim 2 in which the load elementcomprises an undoped polysilicon resistor.
 5. A low current substratebias generator as in claim 2 in which the substrate of the integratedcircuit is P-type and the load element comprises a serpentine N-typewell.
 6. A low current substrate bias generator as in claim 2 in whichthe substrate of the integrated circuit is N-type and the load elementcomprises a serpentine P-type well.
 7. A low current substrate biasgenerator as in claim 2 in which the load element comprises thedrain-to-source resistance of an FET.
 8. A low current substrate biasgenerator as in claim 1 in which the level shifting circuit comprises aplurality of serially-connected diodes.
 9. A low current substrate biasgenerator as in claim 8 in which at least one of the level shiftingdiodes is a diode-connected P-channel FET.
 10. A low current substratebias generator as in claim 8 in which at least one of the level shiftingdiodes is a diode-connected N-channel FET.
 11. A low current substratebias generator as in claim 1 in which the capacitor comprises an FEThaving a gate, a source, and a drain, the gate forming a first plate ofthe capacitor, and the coupled source and drain forming a second plateof the capacitor.
 12. A low current substrate bias generator as in claim1 in which the value of the capacitor is between five and ten times acombined parasitic capacitance of the load element, level shiftingcircuit, and inverter input.
 13. A low current substrate bias generatoras in claim 1 further comprising a hysteresis circuit element interposedbetween the output of the inverter and the input of the charge pump. 14.A low current substrate bias generator as in claim 1 in which theinverter comprises a hysteresis switching-threshold inverter.
 15. A lowcurrent substrate bias generator as in claim 1 in which the invertercomprises an input switching FET coupled to a load FET, the size of theinput switching FET being at least ten times the size of the load FET.16. A low current substrate bias generator as in claim 1 in which thevalue of the source of supply voltage is a predetermined positive valueand the value of a bias voltage at the bias output node is greater thanthe predetermined positive value.
 17. A low current substrate biasgenerator as in claim 1 in which the value of the source of supplyvoltage is substantially equal to ground and the value of a bias voltageat the bias output node is less than ground.
 18. In a substrate biasgenerator for regulating the magnitude of the nominal voltage of asubstrate layer in an integrated circuit, the bias generator having anominal current requirement and including a bias output node forcoupling to the substrate layer, an intermediate node, a load elementcoupled between the intermediate node and a source of supply voltage, alevel shifting circuit coupled between the intermediate node and thebias output node, charge pump means having an input coupled to theintermediate node and an output coupled to the bias output node, amethod for reducing the current requirement of the bias generator whilemaintaining the regulation of the substrate layer voltage, the methodcomprising:capacitively coupling the voltage at the bias output node tothe intermediate node to turn on the charge pump means and restore thenominal substrate voltage; and selecting the value of the load elementsuch that the current flowing through the load element is less than 5μA.19. A method for reducing the current requirement of the bias generatoras in claim 18 in which the step of capacitively coupling the voltage atthe bias output node to the intermediate node comprises coupling acapacitor between the bias output terminal and the intermediate node.20. A method for reducing the current requirement of the bias generatoras in claim 19 in which the value of the capacitor is sized to bebetween five and ten times the value of a total parasitic capacitanceassociated with the intermediate node.